Senior Mixed Signal Design Engineer
Há 2 dias
**Company Overview**
Synopsys, a leader in the Era of Pervasive Intelligence, is driving innovations that shape our lives. Our technology powers self-driving cars, learning machines, and high-performance silicon chips.
**Job Summary**
We seek a seasoned ASIC Digital Design Staff Engineer to develop cutting-edge mixed-signal designs for next-generation technology. The successful candidate will have a robust understanding of ASIC digital development flows and mixed-signal design.
**Key Responsibilities**
- Review SerDes standards and architecture documents to create analog sub-block specifications
- Refine circuit implementations to achieve optimal power, area, and performance targets
- Propose efficient design and verification strategies using simulator features
- Participate in complex block and/or chip planning and architecture studies
- Implement digital portions of mixed-signal blocks using Verilog
- Engage in behavioral modeling activities using Verilog/SystemVerilog language
**The Impact You Will Have**
You will contribute to the development of innovative mixed-signal designs that drive technological advancements. Your work will enhance the efficiency and quality of our design and verification processes.
**Requirements**
- Bachelor's degree in engineering or applied science
- 3+ years of experience in IC design flows and exposure to Verilog/VHDL
- Proficiency in scripting and programming: Unix Shell, Python, Perl, TCL
- Experience with SystemVerilog, VMM, OVM, or UVM
- Knowledge of MIPI or similar protocols
**What We Offer**
- A competitive salary range: $140,000 - $170,000 per year
- Ongoing professional development opportunities
- A collaborative team environment
**Who We Are Looking For**
Highly organized individuals with excellent English communication skills are encouraged to apply. A willingness to learn new things and adapt to new challenges is essential for success in this role.
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