Senior Physical Design Engineer for Mixed-Signal ICs
Há 4 dias
Job Overview:
">We are seeking a highly skilled Senior Physical Design Engineer to join our team of experienced professionals in Europe. This role will be based in one of our offices in Spain, the Netherlands, or Portugal and will involve on-site work with no remote option available.
The successful candidate will play a key role in the design and implementation of mixed-signal ICs, utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions such as switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for fast-growing portable and non-portable markets.
Key Responsibilities:
- Responsible for physical design, development, & verification of digital / mixed-signal IC's
- Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure
- Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IP's
- Help build an automated environment for RTL-to-PNR using high level languages and devops-like services
Requirements:
- Requires advanced degree in Electrical Engineering/Computer Science or equivalent
- 7+ years of Physical Digital Design experience
- 2+ years of ASIC design, verification, or related work experience
- Good written/verbal communication English skills and strong teamwork collaboration
- Ability to work independently, follow instructions according to design specifications and execute tasks to hit milestones with quality
- Strong knowledge of ASIC development process and digital design techniques
- Experience with programming, scripting and automation languages like Perl/TCL/Unix
- Strong technical abilities & understanding in areas such as Verilog/System Verilog coding, Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners, Multipower domain, signal integrity, & power/IR drop analysis, Linting and CDC requirements, Expertise in both hand-written and tool-driven functional/timing ECO, Physical Design Verification methodology to debug LVS/DRC issues at chip/block level, Industry physical tools: Cadence (preferred) or Synopsys, SOC design including uC design (ARM/RISCV), Digital on top designs using both bottom-up and top-down flows, Hierarchical STA for chip top designs, Advanced nodes below 16nm, FinFET
- Experience with following is desired: Statistical STA, AOCV, SI and noise analysis, Knowledge of power management industry/applications I/F: I2C, SPI, USB, PMBUS, etc, Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, Object oriented programming (Python, Java, etc), VCS: git, svn, Devops, Continuous integration, continuous delivery, FPGA development: Xilinx (preferred), Intel, Lattice, etc
Location:
- Spain: Barcelona
- Netherlands: Enschede/Nijmegen
- Portugal: Porto/Lisbon
Salary:
The estimated salary for this role is €90,000 - €120,000 per annum, depending on experience and qualifications.
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