Senior Pcie/cxl Applications Engineering
2 semanas atrás
- PORTUGAL
- Lisbon, PORTUGAL
- Porto
Job Description and Requirements
At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
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Senior PCIE/CXL Applications Engineering
- The position will provide IIP integration guidance to customers throughout their SoC flow to resolve technical challenges across all the ASIC design cycle (From PCIE/CXL IPs architecture/integration and up to the silicon bringup).
- We are looking for rising STAR who can do a change, motivated engineer with deep ASIC related knowledge and experience who can help our key worldwide customers to integrate our cuttingedge technology PCIE/CXL IPs.
- The position offering opportunity to be part of worldwide diverse team and providing the option to be in the front of cuttingedge knowledge including interacting with worldwide industry experts and leaders.
- Some travels may be required.
Key Qualifications
- Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, SI/PI etc.) or silicon bringup/characterization in a system environment.
- Advanced Lab related experience like ATE and highspeed interface IPs bringup.
- Good communication skills and capabilities to interact with different peers from different geographics.
Preferred Experience
- PCIE/CXL expertise, focusing on specifications knowledge and design verification.
- PCIE related Lab experience, focusing on PCIE silicon debug aspects (e
g :
traces/packets analyzing).
- Technical knowledge with Interface IP such as PCIe, Ethernet Protocols, Specification, Design, Verification, and Implementation.
- Excellent organization skills, multitasking capabilities, strong communication skills and ability to interact with Key customers including industries leaders.
- Proven track record in meeting tight schedules and handling multiple projects concurrently, including proven leadership skills.
- Deep highlevel understanding and proven experience as technical lead in different ASIC design cycles like: HIP/SIP integration into high scale SOCs, Design verification flows, physical implementation including timing closure, SI/PI, Silicon bringup in Lab.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.**
Job Category
- Engineering
Country
- Portugal
Job Subcategory
- Applications Engineering
Hire Type
- Employee
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