Phd Position
Há 5 dias
Offer Description Usual digital neural networks consist of large amounts of matrix-vector or matrix-matrix multiplication operations. Thus, the design of dedicated hardware acceleration circuits for digital neural networks mostly focuses on accelerating these matrix operations.
The involved matrices are often quite large, each with millions or tens of millions of parameters. Thus, the size of these memories of parameters and effective bandwidth with the computation cores are design parameters of paramount importance. It has already been proposed to compress the parameters in memory to reduce the required memory size and bandwidth, generally exploiting the inherent sparsity (values that are zero) within these matrices of parameters.
The generalization of this consideration is quantization: it consists in evaluating how many bits of information are actually needed to represent the different parameters involved in a given neural network model. For inference only, quantizations down to 8-bit integers are now relatively common. Extreme quantizations down to 2 bits, 2-bit ternary numbers, and even binary have been considered with success, even though the impact on accuracy is noticeable. The goal of the work is to improve the efficiency of circuits dedicated to the inference operation. The explored direction is heterogeneous quantization within the layers of neurons. Previous works have revealed that within a given layer of a neural network, only a small fraction of the parameters actually need to be at a relatively high quantization (4 or 8 bits), while most of the values can be quantized very low (1 or 2 bits). To enable pushing low quantization very low without too much impact on accuracy, it is necessary to handle heterogeneous quantification within layers of the given neural networks.
The work consists of:
Study of distribution of different quantizations, and their theoretical impact on quality of results.
Study how to transform the layers of neurons to allow distribution of the different computations onto heterogeneous computing operators.
Design demonstration hardware implementations that dynamically perform the distribution of heterogeneous computations in real-time.
Study compromises between design efficiency and quality of results. Proof of concept implementations on FPGA target will be realized.
Required Qualifications:
Excellent knowledge in architectures of digital circuits.
Solid experience with RTL languages (Verilog or VHDL); VHDL would be a plus.
Recommended Qualifications:
Knowledge in architecture of neural networks.
Knowledge in coding and compression of information, or signal processing.
Experience with manipulation and customization of AI training flows.
Proficiency with English language is highly recommended. Proficiency with French language would be a plus. Interest in technologies of microelectronics and problem-solving would be appreciated.
Specific Requirements:
The position will take place within the offices of the TIMA Laboratory, in Grenoble city.
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