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Há 1 mês
Monolithic Power Systems is seeking a highly skilled Digital Verification Framework Engineer to lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.
The ideal candidate will have strong experience in both RTL and Gate-Level Verification, with proficiency in Digital Verification Industry Languages (UVM, System Verilog) and Standards. Excellent scripting and automation skills using TCL, Python or C/C++ are also essential.
We offer an estimated salary of €120,000 - €150,000 per year, depending on experience, for this exciting role in one of our locations: Germany – Munich, Ottobrunn, Spain – Barcelona, Portugal – Lisbon / Porto, Netherlands – Enschede / Nijmegen.
Job Description:
- Define and lead the development of the Digital Verification framework and infrastructure.
- Develop a UVM and System Verilog based Digital Verification environment.
- VIPs standardization, definition, development and documentation.
- Integration of VIPs into the Project's Digital Verification environment.
- Digital Verification Metrics definition for RTL and Gate-Level Verification.
- Test Plan definition and development.
- Digital Verification Automation and Scripting.
- Regression's infrastructure definition, development and management.
Required Skills and Qualifications:
- PhD/BS/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
- 5+ years of strong experience in both RTL and Gate-Level Verification.
- Proficient in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
- Excellent scripting and automation skills using TCL, Python or C/C++.
- Leadership skills to technically guide the DV Team and mentor Jr. DV Designers.
Benefits:
- A competitive salary and benefits package.
- The opportunity to work on cutting-edge projects.
- A dynamic and supportive team environment.
