Staff Physical Digital Design Engineer

2 semanas atrás

Lisboa, Lisboa, Portugal Monolithic Power Systems Tempo inteiro

Job Role Summary:

We are seeking an experienced Staff Physical Digital Design Engineer to join our team of design engineers. This role will be based in one of our European offices, with no remote work option available.

The successful candidate will be responsible for all aspects of physical design and implementation. Key responsibilities include participating in the establishment of physical design methodologies and flow automation, as well as contributing to the design development team.

As a Physical Design Engineer, you will work on the digital design implementation and verification of mixed-signal ICs using standard EDA tools. Products to be designed and verified include power management and mixed-signal functions.

Key Responsibilities:

  • Responsible for physical design, development, and verification of digital/mixed-signal ICs.
  • Chip and block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, and LVS/DRC to closure.
  • Work closely with digital/analog design teams for physical implementation and custom analog blocks/interfaces/IPs.
  • Help build an automated environment for RTL-to-PNR using high-level languages and DevOps-like services.

Requirements:

  • Requires an advanced degree in Electrical Engineering/Computer Science or equivalent.
  • 7+ years (preferred) of physical digital design experience.
  • 2+ years (preferred) of ASIC design, verification, or related work experience.
  • Good written and verbal communication English skills and strong teamwork collaboration.
  • Ability to work independently, follow instructions according to design specifications, and execute tasks to hit milestones with quality.
  • Strong knowledge of ASIC development processes and digital design techniques.
  • Experience with programming, scripting, and automation languages like Perl/TCL/Unix.
  • Strong technical abilities and understanding in areas such as Verilog/System Verilog coding, synthesis, LEC, CTS, DFT, RC extraction, and STA closure across multiple process corners.
  • Multipower domain, signal integrity, and power/IR drop analysis.
  • Linting and CDC requirements.
  • Expertise in both hand-written and tool-driven functional/timing ECO.
  • Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
  • Industry physical tools: Cadence (preferred) or Synopsys.
  • SOC design including uC design (ARM/RISC-V).
  • Digital on top designs using both bottom-up and top-down flows.
  • Hierarchical STA for chip top designs.
  • Advanced nodes below 16nm, FinFET.
  • Experience with the following is desired: statistical STA, AOCV, SI, and noise analysis.
  • Knowledge of power management industry/applications.
  • I/F: I2C, SPI, USB, PMBUS, etc.
  • Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, Object-Oriented Programming (Python, Java, etc.).
  • VCS: git, svn.
  • DevOps, Continuous Integration, Continuous Delivery.
  • FPGA development: Xilinx (preferred), Intel, Lattice, etc.

Location:

  • Spain: Barcelona.
  • Netherlands: Enschede/Nijmegen.
  • Portugal: Porto/Lisbon.

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