Senior Fpga Architect — Pcie Prototyping
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Synopsys Porto is seeking an experienced FPGA design engineer to drive high-performance PCIe solutions from architecture through timing closure. You will collaborate across hardware, software, and verification teams to deliver reliable FPGA prototypes and meet stringent industry standards.
The role focuses on RTL design in Verilog, multi-clock domains, and PCIe protocol debugging within a dynamic engineering team in Porto.
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