Security Asic Rtl Design Engineer For Ip Cores
Há 1 semana
Porto, Portugal
Synopsys Inc
Tempo integral
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Synopsys Porto is seeking an ASIC Digital Design Engineer focused on RTL design and security-conscious IP development. You will design and verify security IP cores, working with an international team across time zones. Requirements include MSc/PhD in EE or CS and 3+ years in RTL design, SystemVerilog, and ASIC verification. Collaboration on security-driven IP is essential for this role.