Digital Verification Engineer

Há 1 mês

Lisboa, Portugal Https:Www.Energyjobline.ComSitemap.Xml Tempo inteiro

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world --- come join our team and see how YOU can make a difference.
Job Description
MPS is looking for a Digital Verification Engineer to join the Automotive BMS Product Line, focused on solving customers' challenges in Electric Vehicles (EVs). In this position, you will develop the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools.
Responsibilities

UVM and System Verilog based digital verification environment definition and development
Verification IP (VIP) standardization, definition, development and documentation
Integrate VIPs into the digital verification environment
Development of test plans to fully verify all digital requirements in project specification
Development of coverage metrics and test cases to fully cover all test plan items
Digital verification scripting and automation
Regression infrastructure definition, development and management
Close interaction with Senior Digital and Analog Designers to develop VIP models and test cases
Lead and supervise digital verification tasks of multiple projects
Analyze and debug test results, code coverage and functional coverage
Digital verification estimation, planning and scheduling to meet tape-out dates

Qualifications

Requires BSEE/MSEE or Equivalent with emphasis in digital design/VLSI coursework
5+ years of experience in both RTL and gate-level verification
Proficient in digital verification industry languages (UVM, System Verilog) and standards
Proficient level in DV skills: constraint randomization, SV assertions, coverage metrics, analog and digital DV modeling, DV test plans, and regression analysis
Skilled with scripting languages such as C shell, Bash, TCL, Python or Perl
Strong knowledge in verification of low power and multiple power domain designs
Experience with digital design, including RTL coding in System Verilog, digital synthesis, timing closure and power estimation
Good written/verbal communication skills and strong teamwork/collaboration
Self-motivated with attention to detail
Strong analytical and problem-solving skills with ability to think outside the box

Knowledge/Experience in the following areas is a plus:

Embedded designs and/or firmware development
Knowledge of functional safety requirements for automotive parts (ASIL)
Experience with Formal Verification tools such as Synopsys VC Formal or Cadence Jasper Gold

Location

Germany – Munich, Ottobrunn
Spain – Barcelona
Portugal – Lisbon / Porto
Netherlands – Enschede / Nijmegen
Phoenix, AZ

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