Senior ASIC Digital Verification Engineer
Há 6 dias
Job Summary
Seeking a highly motivated and innovative ASIC Digital Verification engineer to work as part of a highly experienced mixed-signal design and verification team. The team targets the current and next generation of USB/Pcie/DPHY/CDPHY/MPHY/DisplayPort/HDMI/SATA/Ethernet products for mobile phones, automotive industry, drones, IoT, and other consumer markets.
Main Responsibilities
Work in a Digital and Verification R&D team contributing to the development and validation of complex digital mixed-signal circuits for high-speed interface IP. Define, develop, and support complex verification environments using latest standards methodologies: System Verilog, UVM, and Formal verification. Contribute to meet verification coverage metrics targets. Create verification test plan, verification environment documentation, and test environment usage documentation. Review SerDes standards and architecture documents to develop verification sub-block specifications. Participate in the behavioral modeling activities using Verilog/SystemVerilog language.
Key Requirements
University degree in electronics engineering, computer science, or similar. Experience in producing good technical documentation. Good communication and organizational skills. Good knowledge of both written and spoken English. Willingness to learn new things. Demonstrate good problem-solving skills. Proficiency in at least one programming language such as Python, Perl, C, C++, or MatLab. Understanding of IC design flows and analog circuit design would be advantageous. Understanding of Verilog/System Verilog language would be advantageous. Understanding of a verification methodology such as UVM is a plus.
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