Senior Verification Engineer for Advanced Technologies
4 semanas atrás
As a Senior Verification Engineer at Capgemini, you will be responsible for leading the definition, execution, and continuous enhancement of a robust design verification (DV) methodology and tool flow across various verification platforms.
Your Responsibilities- Taking ownership of IP and SoC verification in both prototype and design environments.
- Establishing functional and performance benchmarks to guide development.
We are looking for an experienced engineer with a solid understanding of System Verilog, as well as substantial experience in constrained random and coverage-driven verification using UVM/OVM.
Your Profile- Degree in Engineering.
- More than 5 years of experience in the field.
- Proficiency in creating UVC components or sequences.
- BASIC KNOWLEDGE OF AT LEAST TWO OF THE FOLLOWING: AHB/AXI, PCIe/CXL, USB, DDR, SERIAL PROTOCOLS, PROCESSOR VERIFICATION, ETC.
- Senior-level positions and above require expertise in at least one protocol.
We offer a competitive salary range of $120,000 - $180,000 per year, depending on your level of experience. You will also have access to valuable training and certifications in cutting-edge technologies, engage in exciting national and international projects, and enjoy a supportive atmosphere promoting work-life balance.
What We Offer- Access to cutting-edge technologies and training programs.
- Opportunities for career growth and professional development.
- A supportive and inclusive team environment.
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