Digital Verification Engineer
Há 4 dias
We are seeking an experienced Staff ASIC Digital Verification Engineer to join our team at Synopsys. The ideal candidate will have a strong background in digital circuit design and verification, with expertise in SystemVerilog and UVM.
Main Responsibilities- Contribute to the development and validation of complex digital circuitry for high-speed interface IP.
- Design, integrate, validate, and verify Test Environment components, sequences, checkers, and coverage according to the mandates of the Verification Plan, Team Methodology, and Group goals and objectives.
- Collaborate with peers and superiors to improve the Test Environment and achieve quality and results.
- Analyze metrics, provide feedback, and plan action.
- Build productive working relationships within the team and across teams and business groups.
- University degree in Electronics Engineering or Computer Science.
- Deep knowledge of IC/Digital Design and Verification flows.
- Comprehensive knowledge of SystemVerilog and UVM.
- Experience with Simulation tools.
- Good problem-solving skills, capable of considering multiple scenarios/approaches.
- Good team-player.
- Good organizational skills.
- Good English skills, both verbal and written.
- 5+ years of relevant experience is highly preferred.
- Experience in SystemVerilog/UVM.
- Proficiency in at least one object-oriented programming language.
- Exposure to Unix, Python, Perl, and TCL scripting.
We offer a competitive salary range of €70,000 - €120,000 per year, depending on experience. Benefits include comprehensive health insurance, retirement plan, and generous paid time off.
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