ASIC Digital Design Engineer

Há 6 dias

Lisboa, Lisboa, Portugal Synopsys Tempo inteiro

Job Description:

We are seeking a highly skilled Digital IC Design Engineer to join our team at Synopsys. As a key member of our Digital and Verification Development team, you will contribute to the development and validation of complex digital mixed signals for high-speed interface IP.

Main Responsibilities:


  • Work in a Digital and Verification Development team contributing to the development and validation of complex digital mixed signals for high-speed interface IP.
  • Understand the IP from a System level, Analog and Digital.
  • Understand ASIC design Flow.
  • Engage in verification activities under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
  • Assemble and implement Subsystem RTL / constraints and DFT architecture for internal subsystems.
  • Have a good understanding of the implementation flows and methodologies for deep sub-micron designs.
  • Prepare and present reports outlining the outcome of technical projects.
  • Have expertise in Verilog RTL coding; Lint/CDC/RDC can be a bonus.
  • Build productive working relationships with different teams across projects.
  • Participate in applicable product/project reviews.

Key Qualifications:

  • University master's degree in electronic/Micro-electronics engineering.
  • Knowledge of IC design flows.
  • Digital design knowledge.
  • Digital tools understanding.
  • Willingness to learn new things.
  • Good team-player.
  • Organizational skills are essential.
  • Good problem-solving skills.
  • Digital signal processing essential.
  • Digital Logic understanding.
  • Good English communication skills.

Preferred Experience:

  • 2+ years of relevant experience is highly preferred.
  • Experience in producing high-quality technical documentation is desirable.
  • Experience with analog tools, preferable Synopsys tools.
  • Good understanding of analog design.
  • Experience in Verilog/VHDL.
  • Proficiency in at least one programming language such as Python, C, C++, and MATLAB.
  • Understanding of System Verilog / VMM / UVM.
  • Exposure to Unix, Perl, and TCL scripting.

About Synopsys:

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things (IOT). These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Synopsys' leading DesignWare IP portfolio is developed by an IP Design Team within Synopsys' Solutions Group. Part of the Team is located in Lisbon and is staffed with analog and digital IC design engineers, application engineers, and test engineers among others. The company's extensive IP portfolio enables next-generation SoC designers to integrate silicon-proven functionality previously available only to large integrated device manufacturers. The IP is licensed to leading semiconductor companies across all major markets, offering high-precision, single-function blocks to complete interface sub-systems. Inclusion and Diversity are important to us.

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