Senior Rtl Engineer: Soc Design

Há 8 horas

Lisbon, Portuguese Republic, Portugal Capgemini Engineering Tempo integral
Capgemini Engineering is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out for high-performance, power-efficient SoCs. You will define microarchitectures, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across verification, synthesis, and physical design teams to ensure timing, power and area targets.
The role requires 6+ years in RTL/ASIC/VLSI, strong HDL skills, and experience with Lint/CDC/Low Power methodologies, STA, and CPU architectures.