Staff ASIC Digital Verification Engineer

3 semanas atrás

Porto, Portugal Landing.jobs Tempo inteiro
At Synopsys Inc (Permanent), in Porto, Portugal Expires at: 2025-02-24 Remote policy: Partial remoteAt Synopsys, we’re at the heart of the innovations that change how we work and play. Self-driving cars, Artificial Intelligence, the cloud, 5G, and The Internet of Things are among the breakthroughs ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP, predesigned blocks of logic, memory, interfaces, analogue, security, and embedded processors -all to help customers integrate more capabilities, meet the unique performance, power, and size requirements of their target applications, and get differentiated products to market quickly with reduced risk. Inclusion and Diversity are essential to us. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability. Synopsys seeks an energetic and detail-oriented

Staff ASIC Digital Verification Engineer

to work with

the

ASIC Digital Design team. Main requirements

Work in a Digital Design and Verification Development team contributing to developing and validating complex digital circuitry for high-speed interface IP. Conceptualize, design, integrate, validate, and verify Test Environment components, sequences, checkers, and coverage according to the mandates of the Verification Plan, Team Methodology, and Group goals and objectives. Debug failures from the Test Environment down to RTL implementation, search and determine root causes, suggest and implement fixes and/or workarounds, and document and track. Collaborate with peers and superiors to help shape and improve the Test Environment to achieve the best quality and results. Guide junior team members in meeting both their and the overall objectives. Analyze metrics, provide feedback and plan of action, and follow through. Build productive working relationships within the team and across teams and business groups. Participate in applicable product/project reviews. Prepare and present reports of Test Plan coverage, Quality of Results, Performance results, etc.

Key Qualifications

University degree in Electronics Engineering or Computer Science Deep Knowledge of IC/Digital Design and Verification flows Comprehensive knowledge of SystemVerilog and UVM Comprehensive experience with Simulation tools Very good problem-solving skills, capable of considering and describing multiple scenarios/approaches Good team-player Good organizational skills Good English skills, both verbal and written.

Preferred Experience

5+ years of relevant experience is highly preferred Experience in SystemVerilog/UVM Proficiency in at least one object-oriented programming language Exposure to Unix, Python, Perl and TCL scripting Experience with collaboration tools like Sharepoint/Teams, Jira/Confluence, P4/Git, etc.

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